Daily Archives: May 28, 2016

Dateline 28/05/2016 “What’s that”

Posted on by 0 comment

George AMG has written a piece on the FPGA in the Ic7300 to help us out.

John and co,

It was with your comments and observations in mind that I read the review of the IC7300 in the latest AR magazine.

Disappointment quickly overwhelmed me as I found error after error in the article.

Firstly however Fig1 is a reasonable representation of the radio in block diagram.




However Fig 2 is misleading in that it shows conventional receiver functions in the DSP block, when really instead of a physical BPF, IF amp, detector,etc these functions are performed by digital “magic” (Software Defined Radio).


Firstly, to comment on the FPGA. The FPGA in this case is a VERY FAST large (in number of possible programmable digital logic functions), devices. The FPGA is clocked by the reference oscillator (could be loosely termed the Local Oscillator). The FPGA may be programmed as microprocessor(s), digital to analog converter (D/A), analog to digital converter (A/D), etc.

On transmit the FPGA generates the RF signal (e.g. SSB, FM, CW, etc) by converting the input audio (from the mic – A/D then DSP) to digital signal, the FPGA mathematically analysing the digital audio and generates the output RF signal at the output frequency by a D/A. The speed of the FPGA and the D/A can be appreciated by realising it will directly generate RF signal up to 75MHz. To achieve this, the internals of the FPGA and the D/A are operating at 8 to 32 times the output frequency. The higher the clock freq to the D/A the better the quality of the output signal.

On receive, the FPGA provides the local oscillator and mixer functions. To make its job easier (suppress strong off frequency signals, some conventional bandpass filtering and amplification occurs between the antenna and A/D (operating at the RF frequency). The digital version of the input signal is processed by the FPGA to two 36kHz digital IF channels (these are termed I & Q and are in 90deg phase). The DSP processes the IQ IF and provides bandwidth limiting and detection of the wanted signal (SSB, FM, CW, etc).

The result is a far lower part count radio. Therefore, it should be cheap to make and more reliable.

From the IQ digital IF signal thru to the speaker is similar most Icom (and other) receivers. On other modern receivers, the conversion to 36kHz IQ IF is performed by phase locked loop (PLL) local oscillators controlled by microprocessors, diode mixers, crystal and LC IF filters.

I hope this helps.

Thanks George I’m sure this is some help to the budding  Ic7300 purchaser.

Category: Official
 NEWS /   Club Meetings. MtGravatt TAFE 7-730pm 2nd Tuesday of the Month.
Powered By : XYZScripts.com